AF201

EW-ESM, LIDAR, Wide-band Receiver
Software Defined Radio

Single Slot FMC HPC
Single channel 12-bit 3 Gsps ADC
Conduction or Air-Cooled

AF201 - EW-ESM, LIDAR, Wide-band ReceiverSoftware Defined Radio  - Apissys

 

Applications

  • Test & Measurement
  • Electronic Warfare
  • Radar Receiver
  • Software Defined Radio

Features

  • 1 channel 12-bit, up to 3 Gsps ADC
  • External clock and reference input
  • Internal low jitter clock generation
  • External trigger input
  • VITA 57 FMC form factor
  • Air cooled and Conduction cooled rugged versions
  • FPGA firmware cores
  • Windows® and Linux® drivers
     

The AF201 is part of ApisSys' range of modular IOs solutions based on the VITA 57, FPGA Mezzanine Card standard.

The AF201 provides customers with a single channel 12-bit up to 3 Gsps ADC capability, ideally suited for test and measurement, Software Defined Radio or Radar Receivers applications.

The AF201 ADC channel is AC coupled with more than 2.3 GHz bandwidth for a full scale signal of 2 dBm (800 mVpp).

 

The AF201 provides an internal ultra low jitter clock generation and can be used with either external clock or external reference for higher flexibility.

The AF201 supports an external trigger signal used to synchronize processing with external events.

The AF201 is fully supported on ApisSys 3U VPX FPGA processing engines, making it ideally suited for test and measurement, Electronic Warfare,

Ultra Wideband Radar Receivers or LIDAR applications.

     

12-bit 2 GSPS Analog to Digital Converter

The AF201 Analog to Digital conversion is performed by a 12-bit 3 Gsps ADC using dual ADC interleaving technologies.
The AF201 provides one front panel MMCX connector for analog input.
Single ended input signal is AC coupled with an input bandwidth from 5 MHz to more than 2.3 GHz with 0 dBm input level.
A wideband signal generator is provided for on board, stand-alone calibration. When used on an ApisSys FMC carrier board such as the AV103 3U VPX Signal Processing Engine, a calibration can be done at power up and/or on customer request with both static and dynamic correction applied for better SFDR.

Clock

The AF201 provides an internal ultra low jitter clock generator locked on a 100 MHz internal reference.
The AF201 provides a front panel MMCX connector for external reference, 10 to 100 MHz, a front panel MMCX connector for an external clock input, from 500 MHz to 3 GHz and a front panel MMCX for an external clock output.
Estimated jitter from the internal clock generation (including 100 MHz reference and clock distribution) is below 200 fs for a 3 GHz clock. Added jitter on external clock is lower than 100 fs.
A dedicated fine clock phase control allows for accurate adjustment of phase delay between both interleaved ADCs.

Trigger and Synchronization

The AF201 provides a front panel MMCX connector for external trigger input.
The trigger synchronization uses the sampling clock divided by 8.

 

FMC interface

The AF201 features a VITA 57 – FMC (FPGA Mezzanine Card) compliant slot.
The FMC uses High Pin Count (HPC) interface with 2.5V or 1.8V Vadj.
The FMC MGT interfaces are unused.

Firmware

The AF201 comes with a firmware package which includes VHDL cores allowing control and communication with all AF201 hardware resources.
A base design is provided which demonstrates the use of the AF201 and gives users a starting point for firmware development.
The AF201 firmware package is supported on the Xilinx ISE® 12 design suite and later versions.
The AF201 firmware package has been fully validated on AV103 and other ApisSys FMC carrier products.

Software

The AF201 is delivered with control software for Windows XP and 7, and Linux, compatible with AV103 and other ApisSys FMC carrier products.
An application example is provided as source code.

Ruggedization

The AF201 is delivered in air cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 supported ruggedization levels are EAC4, EAC6 and ECC3.

     

Analog Input

  • Input coupling: AC
    • Full power bandwidth: > 2.3 GHz
    • Full scale : 2 dBm
  • Impedance: 50 Ohm
  • Connector: MMCX

Analog to Digital Conversion

  • Single channel
  • Resolution: 12 bit
  • Sampling Frequency (assembly option):
    • o 2 GHz or 3 GHz

Sampling Performances

  • 3.0 Gsps, Fin = 500 MHz, -1dBFS:
    • SNR: 56.5 dBFS
    • SFDR: 65 dB
    • THD: 60.5 dB
    • ENOB: 9.0 bits
  • 3.0 Gsps, Fin = 1 GHz, -1dBFS:
    • SNR: 55.5 dBFS
    • SFDR: 64.5 dBc
    • THD: 61 dB
    • ENOB: 8.8 bits

Trigger

  • External: 0 to 2Vp
    • Connector: MMCX

 

 

Clock

  • Internal: 1.0 GHz or 2 GHz low jitter clock (1/2 sampling clock)
    • Internal jitter: < 200 fs
  • External Input Clock:
    • Frequency: 500 MHz to 3.0 GHz
    • Level: 10 dBm to 15 dBm
    • Added jitter: < 100 fs
    • Connector: MMCX, 50 Ohm
  • External Output Clock:
    • Frequency: 1.0 GHz or 2 GHz (1/2 sampling clock)
    • Level: 0 dBm
    • Connector: MMCX, 50 Ohm
  • External reference:
    • Frequency: 10 MHz to 100 MHz
    • Level: 10 dBm to 15 dBm
    • Connector: MMCX, 50 Ohm

FMC interface

  • HPC:
    • LA(0:33): LVDS 2.5V / 1.8V
    • HA(0:23): LVDS 2.5V / 1.8V
    • HB(0:21): LVCMOS 2.5V / 1.8V

Software support

  • Software Drivers:
    • Windows 7
    • Linux
  • Application example:
    • Windows and Linux
 

Firmware support

  • VHDL cores for all hardware resources
  • Base design
  • Supported by Xilinx ISE 14 and later

Ruggedization

  • As per VITA 47:
    • Air cooled : EAC4 and EAC6
    • Conduction cooled : ECC3

Power dissipation

  • +12V: 1.1 A max (12.7W)
  • +3.3V: < 0.1 A
  • VADJ (2.5V): 0.6 A max (1.5W)
  • +3.3VAUX: < 0.1 A

Weight

  • Air cooled : 50g
  • Conduction cooled : 55g
     

r

Part Number   A F 201 - rr - a
Ruggedization level Air Standard - - - - AS - -
  Air Rugged - - - - AR - -
  Conduction Standard - - - - CS - -

Conduction Rugged - - - - CR - -
Options 1 12-bit 2 Gsps ADC - - - - - - 1
  12-bit 3 Gsps ADC - - - - - - 2
     
  Air flow, Standard
AS (VITA 47 EAC4)*
Air flow, Rugged
AR (VITA 47 EAC6)* 
Conduction Standard
CS (VITA 47 ECC3)* 
Conduction Rugged
CR (VITA47 ECC4)*
Operating
Temperature
0°C to +55°C (1)
(8 CFM airfl ow at sea level)
-40 to +70ºC (1)
(8 CFM airfl ow at sea level)
-40°C to +70°C
(Card Edge)
-40°C to +85°C
(Card Edge)
Non Operating Temperature -40°C to +85°C -50°C to +100°C -50°C to +100°C -55°C to +105°C
Operating
Vibration
(Random)
5Hz - 100Hz +3 dB/octave
100Hz-1kHz = 0.04 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.04 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.1 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.1 g2/Hz
1kHz - 2kHz -6 dB/octave
Operating Shock 20g, 11 millisecond, half-sine 20g, 11 millisecond, half-sine 40g, 11 millisecond, half-sine 40g, 11 millisecond, half-sine
Operating
Relative Humidity
0% to 95%
non-condensing
0% to 95%
non-condensing
0% to 95%
non-condensing
0% to 95%
non-condensing
Operating
Altitude
@ 0 to 10,000 ft
with adequate airflow
@ 0 to 30,000 ft
with adequate airflow
@ 0 to 30,000 ft @ 0 to 60,000 ft
Conformal Coating No Optional (default acrylic 1B31) Yes (default acrylic 1B31) Yes (default acrylic 1B31)

*Reference to ANSI-VITA standard VITA 47 (r2) for the listed parameters only. Temperature cycling or other not listed VITA 47 requirements on demand

      architecture of AF201