Real Time Processing, EW, Radar, LIDAR

Virtex 6 FPGA
FMC Carrier, High Pin Count
Conduction or Air-Cooled

AV103 - Real Time Processing, EW, Radar, LIDAR - Apissys



  • Real time processing
  • Electronic Warfare
  • Radar receiver


  • User programmable Xilinx® Virtex® 6 LX195T/SX475T FPGA
  • 350 MHz 2M x 36 QDRII+ SRAM
  • One FMC slot, High Pin Count
  • Embedded microcontroller for monitoring and supervision
  • 3U VPX form factor
  • OpenVPX standard compliant
  • Air cooled and Conduction cooled rugged versions
  • FPGA firmware cores
  • Windows® and Linux® drivers

The AV103 is part of ApisSys' range of High Speed data conversion and signal processing solutions based on the VITA 46, VPX standard.

The AV103 is fully compliant with OpenVPX standard with capabilities to accommodate communication protocols such as PCIe, SRIO, 1Gbit and XAUI 10Gbit Ethernet, as well as non OpenVPX adopted standards such as Aurora or SATA.

The AV103 combines the high processing power delivered by Xilinx® Virtex® 6 FPGA with the flexibility of 3U VPX and FMC mezzanine standards making it ideally suited for embedded signal processing applications such as Electronic Warfare, Ultra Wideband Radar Receivers or LIDAR.


The AV103 includes one Xilinx® Virtex® 6 FPGA LX195T/LX240T/SX315T or SX475T for an impressive processing capability of up to 1 TMACs (Multiply Accumulate per second), one high speed 2M36 QDRII+ SRAM memory for data processing and two FLASH memories for multiple firmware storage.

The AV103 provides a 32-bit microcontroller with USB 2.0 and 10/100 Ethernet interfaces intended to be used for system monitoring and supervision.

The AV103 comes with complete software drivers for Windows and Linux. An FPGA firmware package is provided including all cores necessary to build user FPGA applications.



The AV103 is fitted with a Xilinx Virtex 6 LX195T/LX240T/SX315T or SX475T user programmable FPGA. Only few resources are used to control and communicate with external hardware such as QDRII+ SRAM and monitoring sub-system, leaving most of the logic and block RAM and all DSP resources available for customer processing.
Dedicated to signal processing, the Xilinx Virtex 6 LX195T FPGA includes 199,680 logics cells, 344 bloc RAM (36 Kbit each), 640 DSP48E1 slices, 2 PCIe interface blocs and 4 10/100/1000 Ethernet MAC blocs.
The most powerful version embeds a Xilinx Virtex 6 SX475T which provides 476,160 logics cells, 1,064 bloc RAM and 2,016 DSP48E1 slices for an impressive processing power of up to 1 TMACs.
The FPGA is delivered in -2 speed grade.


The AV103 includes one 2M36 QDRII+ SRAM memory clocked at 350 MHz for a peak data rate of 6.3 GB par second.

FLASH Memory

The AV103 includes one 128 Mbit SelectMAP FLASH memory and one 1 Gbit BPI FLASH used to store multiple FPGA configuration files.

VPX interface

The AV103 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane, one Fat Pipe for Expansion Plane, two Ultra Thin Pipes for Control Plane and two User Defined Ultra Thin Pipes on P1. The AV103 also supports a USB2.0, a 10/100 Ethernet and 28 LVDS differential pairs on P2.

FMC interface

The AV103 features a VITA 57 – FMC (FPGA Mezzanine Card) compliant slot.
The FMC supports High Pin Count (HPC) interface with up to 80 differential signal pairs.
The FMC interface also supports 4 high-speed serial links (FPGA GTXs) running at up to 6.25 Gbit/s in full duplex mode.


GTX Clock Generation

The AV103 features two low phase noise clock generators able to synthesize clock references for the FPGA GTXs from 100 MHz to 312.5 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1 and Gen 2, SATA, SRIO and XAUI 10Gbit Ethernet up to 6.25 Gbps.
An on board EEPROM is used to store the clock generators customer default settings.


The AV103 features a 32-bit 80 MHz microcontroller used primarily for board monitoring and supervision.
The microcontroller supports a USB 2.0 and a 10/100 Ethernet interfaces accessible on the VPX P2 user IO pins through an ApisSys RT101 Rear Transition Module or an ANSI/VITA 46.10 compliant custom RTM board.
The microcontroller firmware includes all necessary features for board monitoring and supervision, including FPGA firmware downloads through Ethernet or USB.


The AV103 comes with a firmware package which includes VHDL cores allowing control and communication with all AV103 hardware resources.
A base design is provided which demonstrates the use of the AV103 and gives users a starting point for firmware development.
The AV103 firmware package is supported on the Xilinx ISE® 12 design suite and later.


The AV103 is delivered with control software for Windows XP and 7, and Linux.
An application example is provided as source code.


The AV103 is delivered in air-cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 supported ruggedization levels are EAC4, EAC6 and ECC3.




  • FPGA: Xilinx Virtex 6
    • XC6VLX195T-2FFG1156 or
    • XC6VLX240T-2FFG1156 or
    • XC6VSX315T-2FFG1156 or
    • XC6VSX475-2FFG1156


  • 1 bank 2M x 36-bit QDRII+ SRAM, 350 MHz clock
  • 128 Mbit Platform Flash XL used in Slave SelectMap mode
  • One 1 Gbit NOR FLASH memory used in 8-bit BPI mode


  • 32-bit PIC32 with 512 MB FLASH
  • Board configuration and monitoring
  • USB2.0 interface on VPX P2
  • 10/100 Ethernet on VPX P2
  • Power supply and Temperature monitoring
  • I2C interface on VPX (SMbus) and
  • FMC

VPX interface

  • P1:
    • Data plane: two fat pipes
    • Expansion plane: one fat pipe
    • Control plane: two ultra-thin pipes
    • Two user-defined ultra-thin pipes
  • P2:
    • USB2.0 and 10/100 Ethernet
    • 28 LVDS differential pairs

FMC interface

  • 2.5V or 1.5V VADJ, default to 2.5V
  • HPC: 80 differential pairs:
    • LA(0:33): default to LVDS
    • HA(0:23): default to LVDS
    • HB(0:21): default to LVDS
  • 4 MGT up to 6.25 Gbps

Firmware support

  • VHDL cores for all hardware resources and Base design
  • Supported by Xilinx ISE 14 and later

Software support

  • Software Drivers:
    • Windows 7
    • Linux
  • Application example:
    • Windows and Linux


  • As per VITA 47:
    • Air cooled : EAC4 and EAC6
    • Conduction cooled : ECC3
    • Conduction cooled : ECC4 consult factory

n Power

  • +12V: 2.4 A max (28.8W)
  • +5V: 3 A max (15W)
  • +3.3V: 0.5 A max (1.7W)
  • +3.3VAUX: 0.3 A max (0.9W)


Air cooled : 400g
Conduction cooled : 400g



Part Number   A V 103 - rr - a
Ruggedization level Air Standard - - - - AS - -
  Air Rugged - - - - AR - -
  Conduction Standard - - - - CS - -

Conduction Rugged - - - - CR - -
Options 1 FPGA Virtex 6 LX195T-2 - - - - - - 1
  FPGA Virtex 6 LX240T-2 - - - - - - 2
  FPGA Virtex 6 SX315T-2 - - - - - - 3
  FPGA Virtex 6 SX475T-2 - - - - - - 4
  Air flow, Standard
AS (VITA 47 EAC4)*
Air flow, Rugged
AR (VITA 47 EAC6)*
Conduction Standard
CS (VITA 47 ECC3)*
Conduction Rugged
0°C to +55°C (1)
(8 CFM airfl ow at sea level)
-40 to +70ºC (1)
(8 CFM airfl ow at sea level)
-40°C to +70°C
(Card Edge)
-40°C to +85°C
(Card Edge)
Non Operating Temperature -40°C to +85°C -50°C to +100°C -50°C to +100°C -55°C to +105°C
5Hz - 100Hz +3 dB/octave
100Hz-1kHz = 0.04 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.04 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.1 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.1 g2/Hz
r 1kHz - 2kHz -6 dB/octave
Operating Shock 20g, 11 millisecond, half-sine 20g, 11 millisecond, half-sine 40g, 11 millisecond, half-sine 40g, 11 millisecond, half-sine
Relative Humidity
0% to 95%
0% to 95%
0% to 95%
0% to 95%
@ 0 to 10,000 ft
with adequate airflow
@ 0 to 30,000 ft
with adequate airflow
@ 0 to 30,000 ft @ 0 to 60,000 ft
Conformal Coating No Optional (default acrylic 1B31) Yes (default acrylic 1B31) Yes (default acrylic 1B31)

*Reference to ANSI-VITA standard VITA 47 (r2) for the listed parameters only. Temperature cycling or other not listed VITA 47 requirements on demand

      architecture of AV103