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10-bit 3 GSPS ADC
The AV104 Analog to Digital conversion is performed by two 10-bit 3 Gsps ADCs.
The AV104 provides two front panel SSMC connectors for analog input.
Single ended input signals are AC coupled with an input bandwidth of 5 MHz to 4 GHz with 2 dBm input level.
12-bit 3 GSPS DAC
The AV104 Digital to Analog conversion is performed by one 12-bit 3 Gsps ADCs.
The AV104 provides one front panel SSMC connector for analog output. Single ended output signal is AC coupled with an output bandwidth of 5 MHz to 4 GHz with -2 dBm output level.
Clock
The AV104 provides an internal ultra low jitter clock generator locked on a 100 MHz internal reference.
The AV104 provides a front panel SSMC connector for a 10 to 100 MHz external reference, a front panel SSMC connector for a 500 MHz to 3 GHz external clock input, and a front panel SSMC connector for an external clock output.
Estimated jitter from the internal clock generation (100 MHz reference and clock distribution) is below 200 fs for a 3 GHz clock. Added jitter on external clock is lower than 100 fs.
Trigger and Synchronization
The AV104 provides a front panel SSMC connector for external trigger input. The trigger synchronization uses the sampling clock divided by 8.
FPGA
The AV104 is fi tted with a Xilinx Virtex 7VX330T/VX485T or VX690T user programmable FPGA. Only few resources are used to control and communicate with external hardware such as QDRII+ SRAM and monitoring sub-system, leaving most of the logic and block RAM and all DSP resources available for customer processing.
Dedicated to signal processing, the Xilinx Virtex 7 VX485T FPGA includes 485,760 logics cells, 1,030 bloc RAM (36 Kbit each), 2800 DSP48E1 slices and 2 PCIe interface blocs.
The most powerful version embeds a Xilinx Virtex 7 VX690T which provides 693,120 logics cells, 1,470 bloc RAM and 3,600 DSP48E1 slices for an impressive processing power of more than 2 TMACs.
The FPGA is delivered in -2 speed grade.
QDRII+ SRAM Memory
The AV104 includes one 2M36 QDRII+ SRAM memory clocked at 500 MHz for a peak data rate of 9 GB/s.
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FLASH Memory
The AV104 includes one 1 Gbit synchronous BPI FLASH used to store multiple FPGA configuration files.
VPX interface
The AV104 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane, one Fat Pipe for Expansion Plane, two Ultra Thin Pipes for Control Plane and two User Defi ned Ultra Thin Pipes on P1. The AV104 also supports a USB2.0, a 10/100 Ethernet and 24 LVDS differential pairs on P2.
The AV104 features two low phase noise clock generators able to synthesize clock references for the FPGA GTXs from 100 MHz to 312.5 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1 and Gen 2, SATA, SRIO and XAUI 10Gbit Ethernet up to 12.5 Gbps.
Microcontroller
The AV104 features a 32-bit 80 MHz microcontroller used primarily for board monitoring and supervision.
The microcontroller supports USB 2.0 and 10/100 Ethernet interfaces accessible on the VPX P2 user IO pins through an ApisSys AR102 Rear Transition Module or an ANSI/VITA 46.10 compliant custom RTM board.
The microcontroller fi rmware includes all necessary features for board monitoring and supervision, including FPGA fi rmware downloads through Ethernet or USB.
Firmware
The AV104 comes with a firmware package which includes VHDL cores allowing control and communication with all AV104 hardware resources.
A base design is provided which demonstrates the use of the AV104 and gives users a starting point for fi rmware development. The AV104 firmware package is supported on the Xilinx ISE® 14 design suite and later.
Software
The AV104 is delivered with control software for Windows 7, and Linux.
Ruggedization
The AV104 is delivered in air-cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 supported ruggedization levels are EAC4, EAC6, ECC3 and ECC4.
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