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Quad Small Form-Factor Pluggable Transceiver
The AV109 supports three independent Quad Small Form-Factor Pluggable (QSFP) transceivers.
The AV109 supports optical QSFP transceivers for communication at up to 120 Gbps over distances up to 10 km.
The AV109 supports copper QSFP transceivers for communication at up to 120 Gbps over distances up to a few meters.
Clocks
The AV109 provides three on-board, user programmable, low jitter clock generator generating clock references as required for the high speed serial links (Xilinx Virtex® 7 GTH).
The clock frequency can be selected among the following:
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100 MHz, supporting PCIe gen 1
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106.25 MHz, supporting Serial FPDP and Fibre Channel
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125 MHz, supporting PCIe gen 1, GigE, Aurora and SRIO 1.25 and 2.5 Gbps
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150 MHz, supporting SATA
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156.25 MHz, supporting XAUI, SRIO and Aurora 3.125 Gbps
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159.375 MHz, supporting 10-G Fibre Channel
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250 MHz, supporting PCIe gen 2
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312.5 MHz, supporting Aurora 5 and 6.25 Gbps
FPGA
The AV109 is fi tted with a Xilinx Virtex 7 VX415T or VX690T user programmable FPGA. Only few resources are used to control and communicate with external hardware such as DDR3 SDRAM and monitoring subsystem, leaving most of the logic and block RAM and all DSP resources available for customer processing.
Dedicated to signal processing, the Xilinx Virtex 7 VX415T FPGA includes 412,160 logics cells, 880 bloc RAM (36 Kbit each), 2,160 DSP48E1 slices and 2 PCIe interface blocs.
The most powerful version embeds a Xilinx Virtex 7 VX690T which provides 693,120 logics cells, 1,470 bloc RAM and 3,600 DSP48E1 slices for an impressive processing power of more than 2 TMACs.
The FPGA is delivered in -2 speed grade.
FLASH Memory
The AV109 includes two 667 MHz 256M16 DDR3 SDRAM memory banks and one 1 Gbit synchronous BPI FLASH used to store multiple FPGA confi guration files.
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VPX interface
The AV109 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane, one Fat Pipe for Expansion Plane, two Ultra Thin Pipes for Control Plane and two User Defi ned Ultra Thin Pipes on P1. The AV109 also supports a USB2.0, a 10/100 Ethernet and 24 LVDS differential pairs on P2.
The AV109 features two low phase noise clock generators able to synthesize clock references for the FPGA GTXs from 100 MHz to 312.5 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1 and Gen 2, SATA, SRIO and XAUI 10Gbit Ethernet up to 12.5 Gbps.
Microcontroller
The AV109 features a 32-bit 80 MHz microcontroller used primarily for board monitoring and supervision.
The microcontroller supports USB 2.0 and 10/100 Ethernet interfaces accessible on the VPX P2 user IO pins through an ApisSys AR102 Rear Transition Module or an ANSI/VITA 46.10 compliant custom RTM board.
The microcontroller fi rmware includes all necessary features for board monitoring and supervision, including FPGA fi rmware downloads
through Ethernet or USB.
Firmware
The AV109 comes with a fi rmware package which includes VHDL cores allowing control and communication with all AV109 hardware resources.
A base design is provided which demonstrates the use of the AV109 and gives users an starting point for fi rmware development. The AV109 firmware package is supported on the Xilinx VIVADO® 2012.4 design suite and later.
Software
The AV109 is delivered with control software for Windows 7 and Linux.
Ruggedization
The AV109 is delivered in air-cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 supported ruggedization levels are EAC4, EAC6, ECC3 and ECC4.
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