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Quad Small Form-Factor Pluggable Transceiver
The AV112 supports one Quad Small Form-Factor Pluggable (QSFP) transceivers.
The AV112 supports optical QSFP transceivers for communication at up to 40 Gbps over distances up to 10 km.
The AV112 supports copper QSFP transceivers for communication at up to 40 Gbps over distances up to a few meters.
Clocks
The AV112 provides one on-board, user programmable, low jitter clock generator generating clock references as required for the high speed serial links (Xilinx Virtex® 7 GTH).
The clock frequency can be selected among the following:
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62.5 MHz, supporting GigE
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75 MHz and 150 MHz, supporting SATA
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100 MHz, supporting PCIe gen 1
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106.25 MHz, supporting Serial FPDP and Fibre Channel
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125 MHz, supporting PCIe gen 1, GigE, Aurora and SRIO 1.25 and 2.5 Gbps
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156.25 MHz, supporting XAUI, SRIO and Aurora 3.125 Gbps
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159.375 MHz, supporting 10-G Fibre Channel
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200 MHz and 250 MHz, supporting PCIe gen 2
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212.5 MHz, supporting 4-G Fibre Channel
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312.5 MHz, supporting Aurora 5 and 6.25 Gbps
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625 MHz, supporting 10 GigE
FPGA
The AV112 is fitted with a Xilinx Virtex 7 VX690T or VX980T user programmable FPGA. Only few resources are used to control and communicate with external hardware such as DDR3 SDRAM and monitoring subsystem, leaving most of the logic and block RAM and all DSP resources available for customer processing.
Dedicated to signal processing, the Xilinx Virtex 7 VX690T FPGA includes 693,120 logics cells, 1,470 bloc RAM (36 Kbit each), 3,600 DSP48E1 slices and 3 PCIe interface blocs.
The most powerful version embeds a Xilinx Virtex 7 VX980T which provides 979,200 logics cells, 1,500 bloc RAM and 3,600 DSP48E1 slices for an impressive processing power of more than 2 TMACs.
The FPGA VX690T is delivered in -2 speed grade while the VX980T is delivered in -1 speed grade.
Memory
The AV112 includes two 667 MHz 256M64 DDR3 SDRAM memory banks (500 MHz for the VX980T version) and one 1 Gbit synchronous BPI FLASH used to store multiple FPGA configuration files.
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VPX Interface
The AV112 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane, one Fat Pipe for Expansion Plane, two Ultra Thin Pipes for Control Plane and two User Defi ned Ultra Thin Pipes on P1. The AV112 also supports a USB2.0, a 10/100 Ethernet and 28 LVDS differential pairs on P2.
The AV112 features two low phase noise clock generators able to synthesize clock references for the FPGA GTXs from 100 MHz to 312.5 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1 and Gen 2, SATA, SRIO and XAUI 10Gbit Ethernet up to 12.5 Gbpss.
Microcontroller
The AV112 features a 32-bit 80 MHz microcontroller used primarily for board monitoring and supervision.
The microcontroller supports USB 2.0 and 10/100 Ethernet interfaces accessible on the VPX P2 user IO pins through an ApisSys AR102 Rear Transition Module or an ANSI/VITA 46.10 compliant custom RTM board.
The microcontroller firmware includes all necessary features for board monitoring and supervision, including FPGA fi rmware downloads through Ethernet or USB.
Firmware
The AV112 comes with a firmware package which includes VHDL cores allowing control and communication with all AV112 hardware resources.
A base design is provided which demonstrates the use of the AV112 and gives users an starting point for firmware development. The AV112 firmware package is supported on the Xilinx VIVADO® 2012.4 design suite and later.
Software
The AV112 is delivered with control software for Windows 7 and Linux.
Ruggedization
The AV112 is delivered in air-cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 supported ruggedization levels are EAC4, EAC6, ECC3 and ECC4.
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