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14-bit 1.25 Gsps Analog-Digital Converters
The AV113 Analog to Digital conversion is performed by eight 14-bit 1.25 Gsps ADCs each with two independent Digital Down Converters.
The AV113 provides eight front panel SMPM connectors for analog inputs.
Single ended input signals are AC coupled with an input bandwidth from 1 MHz to more than 2.3 GHz with 10 dBm input level.
A wideband signal generator is provided for on board, stand-alone calibration.
Clock
The AV113 provides four independent ultralow jitter clock synthesizers locked on a 100 MHz internal reference.
The AV113 provides a front panel SMPM connector for external reference, 10 to 100 MHz as well as a VPX P2 reference input.
The VPX P2 connector supports external clock inputs for the ADCs and clock output when the internal clock synthesizers are used. External clock from 500 MHz to 1.25 GHz are supported.
Dedicated fine clock phase controls on each channel allow for accurate adjustment of phase delay between all channels.
Trigger and Synchronization
The AV113 support a differential pair on VPX P2 connector used a trigger signal. An embedded Time do Digital Converter with a 15ps resolution allow for fine synchronisation on external event.
FPGA
The AV113 is fitted with a Xilinx Virtex 7 VX415T or VX690T user programmable FPGA. Only few resources are used to control and communicate with external hardware such as DDR3 SDRAM and monitoring subsystem, leaving most of the logic and block RAM and all DSP resources available for customer processing.
Dedicated to signal processing, the Xilinx Virtex 7 VX415T FPGA includes 412,160 logics cells, 880 bloc RAM (36 Kbit each), 2,160 DSP48E1 slices and 2 PCIe interface blocs.
The most powerful version embeds a Xilinx Virtex 7 VX690T which provides 693,120 logics cells, 1,470 bloc RAM and 3,600 DSP48E1 slices for an impressive processing power of more than 2 TMACs.
The FPGA is delivered in -2 speed grade.
Memories
The AV113 includes one 667 MHz 256M64 DDR3 SDRAM memory banks and one 1 Gbit synchronous BPI FLASH used to store multiple FPGA configuration files.
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VPX interface
The AV113 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane, one Fat Pipe for Expansion Plane, two Ultra Thin Pipes for Control Plane and two User Defined Ultra Thin Pipes on P1. The AV113 also supports a USB2.0, a 10/100 Ethernet and 16 LVDS differential pairs on P2.
The AV113 features two low phase noise clock generators able to synthesize clock references for the FPGA GTHs from 100 MHz to 312.5 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1 and Gen 2, SATA, SRIO and XAUI 10Gbit Ethernet up to 12.5 Gbps.
Microcontroller
The AV113 features a 32-bit 80 MHz microcontroller used primarily for board monitoring and supervision.
The microcontroller supports a USB 2.0 and a 10/100 Ethernet interfaces accessible on the VPX P2 user IO pins through an ApisSys AR102 Rear Transition Module or an ANSI/VITA 46.10 compliant custom RTM board.
The microcontroller firmware includes all necessary features for board monitoring and supervision.
Firmware
The AV113 comes with a firmware package which includes VHDL cores allowing for control and communication with all AV113 hardware resources.
A base design is provided which demonstrates the use of the AV113 and gives users a starting point for firmware development. The AV113 firmware package is supported on the Xilinx VIVADO® 2013.4 design suite and later.
Software
The AV113 is delivered with software drivers for Windows 7 and Linux.
Ruggedization
The AV113 is delivered in air cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 supported ruggedization levels are EAC4, EAC6, ECC3 and ECC4.
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