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12-bit 5.4 Gsps Analog-Digital Converter
The AV125 Analog to Digital conversion is performed by one e2v EV12AS350 12-bit 5.4 Gsps ADC.
The AV125 provides one front panel SMPM connector for analog input.
Single ended input signal is AC coupled with an input bandwidth from 1 MHz to more than 5.5 GHz with 8.5 dBm input level.
12-bit 5.4 Gsps Digital-Analog Converter
The AV125 Digital to Analog conversion is performed by one e2v EV12DS460 12-bit 6 Gsps DAC.
The AV125 provides one front panel SMPM connector for analog output.
Single ended output signal is AC coupled with an output bandwidth from 1 MHz to more than 6 GHz with -3.5 dBm output level (NRZ)
Clock
The AV125 provides one ultra-low jitter clock synthesizer locked on a 100 MHz internal reference.
The AV125 supports a 10 to 800 MHz external reference input either from a front panel SMPM connector or from the VPX P2 Connector.
External clock inputs for the ADC and DAC are supported from either one SMPM connector or VPX P2. External clock from 2.0 GHz to 5.4 GHz are supported.
External clock outputs are provided on an SMPM connector and on VPX P2.
Trigger and Synchronization
The AV125 provides one front panel SMPM connector for external trigger input and one SMPM connector for a trigger output.
FPGA
The AV125 is fitted with a Xilinx® Kintex® Ultrascale™ KU115 user programmable FPGA. Only few resources are used to control and communicate with external hardware such as DDR3 SDRAM and monitoring sub-system, leaving most of the logic and block RAM and all DSP resources available for customer processing.
Dedicated to signal processing, the Xilinx Kintex Ultrascale KU115 FPGA includes 1,451 K logics cells, 2,160 36 Kbit RAM blocs, 6 PCIe interface blocs and 5,520 DSP48 slices for an impressive processing power of more than 7 TMACs.
The FPGA is delivered in -2 speed grade.
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Memories
The AV125 includes two 800 MHz 256M64 DDR3 SDRAM memory banks and two 1 Gbit QSPI FLASH used to store multiple FPGA configuration files.
VPX interface
The AV125 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane, one Fat Pipe for Expansion Plane, two Ultra-Thin Pipes for Control Plane and two User Defined Ultra-Thin Pipes on P1. The AV125 also supports 26 LVCMOS33 signals and 4 SUB-LVDS differential pairs on P2 plus USB2.0 and 10/100 Ethernet for supervision and monitoring.
The AV125 features two low phase noise clock generators able to synthesize clock references for the FPGA GTHs from 60 MHz to 820 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1, 2 and 3, SATA, SRIO and XAUI 10Gbit Ethernet up to 16.375 Gbps.
Microcontroller
The AV125 features a 32-bit 80 MHz microcontroller used primarily for board monitoring and supervision.
The microcontroller supports a USB 2.0 and a 10/100 Ethernet interfaces accessible on the VPX P2 user IO pins through an ApisSys AR102 Rear Transition Module or an ANSI/VITA 46.10 compliant custom RTM board.
The microcontroller firmware includes all necessary features for board monitoring and supervision.
Firmware
The AV125 comes with a firmware package which includes VHDL cores allowing for control and communication with all AV125 hardware resources.
A base design is provided which demonstrates the use of the AV125 and gives users a starting point for firmware development. The AV125 firmware package is supported on the Xilinx VIVADO® 2016.2 design suite and later.
Software
The AV125 is delivered with software drivers for Windows 7 and Linux.
Ruggedization
The AV125 is delivered in air cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 supported ruggedization levels are EAC4, EAC6, ECC3 and ECC4.
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